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REAL-TIME CLOCK
RP/ RF/ RS5C62
APPLICATION MANUAL
ELECTRONIC DEVICES DIVISION
NO.EA-012-9803
NOTICE
1. The products and the product specifications described in this application manual are subject to change or discontinuation of production without notice for reasons such as improvement. Therefore, before deciding to use the products, please refer to Ricoh sales representatives for the latest information thereon. 2. This application manual may not be copied or otherwise reproduced in whole or in part without prior written consent of Ricoh. 3. Please be sure to take any necessary formalities under relevant laws or regulations before exporting or otherwise taking out of your country the products or the technical information described herein. 4. The technical information described in this application manual shows typical characteristics of and example application circuits for the products. The release of such information is not to be construed as a warranty of or a grant of license under Ricoh's or any third party's intellectual property rights or any other rights. 5. The products listed in this document are intended and designed for use as general electronic components in standard applications (office equipment, computer equipment, measuring instruments, consumer electronic products, amusement equipment etc.). Those customers intending to use a product in an application requiring extreme quality and reliability, for example, in a highly specific application where the failure or misoperation of the product could result in human injury or death (aircraft, spacevehicle, nuclear reactor control system, traffic control system, automotive and transportation equipment, combustion equipment, safety devices, life support system etc.) should first contact us. 6. We are making our continuous effort to improve the quality and reliability of our products, but semiconductor products are likely to fail with certain probability. In order prevent any injury to persons or damages to property resulting from such failure, customers should be careful enough to incorporate safety measures in their design, such as redundancy feature, fire-containment feature and fail-safe feature. We do not assume any liability or responsibility for any loss or damage arising from misuse or inappropriate use of the products. 7. Anti-radiation design is not implemented in the products described in this application manual. 8. Please contact Ricoh sales representatives should you have any questions or comments concerning the products or the technical information.
June 1995
RP/RF/RS5C62
APPLICATION MANUAL
CONTENTS
......................................................................................................1 FEATURES....................................................................................................1 BLOCK DIAGRAM .........................................................................................1 PIN CONFIGURATION ...................................................................................2 PIN DESCRIPTION ........................................................................................2 ABSOLUTE MAXIMUM RATINGS ...................................................................3 RECOMMENDED OPERATING CONDITION ....................................................3 DC ELECTRICAL CHARACTERISTICS ...........................................................4 AC ELECTRICAL CHARACTERISTICS ...........................................................5 TIMING CHART .............................................................................................5 FUNCTIONAL DESCRIPTION.........................................................................6 1. Addressing.................................................................................................6 2. Functions of Registers ...................................................................................7 3. Functions of Counters ..................................................................................15 USAGE ........................................................................................................17 1. Reading and Writing Operations ......................................................................17 2. Handling of CE Pin ......................................................................................18 3. Configuration of Oscillatory Circuit ....................................................................19 4. Adjustment of Oscillation Frequencies ...............................................................20 5. Interrupts .................................................................................................22 6. Timer......................................................................................................23 7. Detection of Stop of Oscillation........................................................................24 8. Typical Power Supply Circuit ...........................................................................25 9. Typical Connection between RP/RF/RS5C62 and CPU ...........................................26 10. Typical Characteristics..................................................................................27 11. Typical Software-controlled Processes ...............................................................29
OUTLINE
QUESTIONS AND ANSWERS ON USE .........................................................34 PACKAGE DIMENSIONS ..............................................................................42 TAPING SPECIFICATIONS ...........................................................................43
REAL-TIME CLOCK
RP/RF/RS5C62
OUTLINE
The RP/RF/RS5C62 are CMOS LSIs which serve microcomputers as real-time clocks providing time, calendar, and alarm functions in direct coupling with the data buses of CPUs such as 8086 and 68000. A built-in timer counter acts as a watchdog timer or interrupt timer. They are available in three different types of packages: the DIP type, the SOP type, and the SSOP type.
FEATURES
* Directly connected to CPU, enabling fast access. * 4bit bidirectional data bus, and 4bit address bus. * The oscillator is driven by a constant voltage, so the oscillation frequency is stable even when the power supply voltage fluctuates. * Built-in timer counter using internal clock. * Generates cyclic CPU interrupts, and generates alarm-match interrupts. * Interrupt flag and interrupt inhibit. * Clock (hour, minute, second), calendar (leap year, year, month, day, day-of-the-week), alarm (hour, minute). * 12-or 24-hour mode is selectable. * Recognizes leap years automatically. * All clock and alarm data expressed in BCD codes. * 30 seconds adjustment function. * Determines whether clock data is valid or invalid. * Consumes very low power due to CMOS technology, so it can be backed up by batteries. * Power supply voltage between 3.0 to 5.0V. * Time keeping supply voltage between 2.0 to 6.0V. * Package : 18pin DIP for RP5C62, 18pin SOP for RF5C62, 20pin SSOP for RS5C62.
BLOCK DIAGRAM
OSCIN OSCOUT OSC DIV
WATCH & CALENDAR OSC DETECT COMPARATOR
INTERRURT CONTROL
INTR
CE CS
ALARM REGISTER
TMOUT RD WR
CONTROL REGISTER TIMER
DATA BUS CONTROL
ADDRESS BUS CONTROL
ADDRESS DECODER
VDD VSS
D0D1D2 D3
A0 A1 A2 A3
1
RP/RF/RS5C62
PIN CONFIGURATION
* RP5C62 (18pin DIP)
1 CS CE TMOUT A0 A1 A2 A3 RD VSS 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VDD OSCOUT OSCIN INTR D3 D2 D1 D0 WR CS CE TMOUT A0 A1 A2 A3 RD VSS 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 CS VDD CE OSCOUT TMOUT OSCIN NC INTR A0 D3 A1 D2 A2 D1 A3 D0 RD WR VSS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD OSCOUT OSCIN NC INTR D3 D2 D1 D0 WR
* RF5C62 (18pin SOP)
* RS5C62 (20pin SSOP)
PIN DESCRIPTION
Pin No. Symbol Name Function
1 2
CS CE
Chip select input Chip enable input
CS and CE are used when interfacing external devices. They may be accessed when CS is low and CE is high. CE is connected to an output of power down detector on the system power supply side, and CS is connected to the microcomputer address bus. Timer output may be used as an interrupt free-run timer or watchdog timer. When CE is low (running on battery backup), operation stops (there is no output). It is N-ch open drain output. Address input is connected to the CPU address bus. It is gated internally with CE. When RD falls from high to low, the contents of the counters or registers specified by A0 to A3 are output to D0 to D3. It is valid when CS is low and CE is high. It is CMOS input. When WR falls from high to low or rises from low to high, the contents of D0 to D3 are written to registers or counters specified by A0 to A3. WR is valid when CS is low and CE is high. It is CMOS input. D0 to D3 are connected to the CPU data bus. The input section is gated internally with CE. It is CMOS input/output. INTR outputs cyclic interrupts or alarm interrupts to CPU. It also operates when CE is low (at battery backup). It is N-ch open drain output. Crystal oscillator of 32.768kHz must be connected between OSCIN and OSCOUT. Capacitance is connected externally between VDD and OSCIN and VDD and OSCOUT, forming the oscillator circuit. VDD connects to +5V or +3V and VSS to ground.
3
TMOUT
Timer output
4-7
A0 -A3
Address input
8
RD
Read control input
10
WR
Write control input
11-14
D0-D3
Bi-directional data bus Interrupt output
15
INTR
16 17 18 9
OSCIN OSCOUT VDD VSS
Oscillator circuit input/output
Power supply
*)
The pin numbers marked in the above table indicate the pins on the 18pin packages.
2
RP/RF/RS5C62
ABSOLUTE MAXIMUM RATINGS
Symbol Item Conditions Ratings
VSS=0V
Unit
VDD VI VO PD Topt Tstg
Supply Voltage Input Voltage Output Voltage 1 Output Voltage 2 Maximum Power Dissipation Operating Temperature Storage Temperature INTR, TMOUT Except INTR, TMOUT TA=25C
-0.3 to +7.0 -0.3 to +VDD+0.3 -0.3 to +12.0 -0.3 to +VDD+0.3 300 -20 to +70 -40 to +125
V V V V mW C C
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum ratings are threshold limit values that must not be exceeded even for an instant under any conditions. Moreover, such values for any two items must not be reached simultaneously. Operation above these absolute maximum ratings may cause degradation or permanent damage to the device. These are stress ratings only and do not necessarily imply functional operation below these limits.
RECOMMENDED OPERATING CONDITION
VSS=0V, Topt=-20 to +70C
Limits Symbol Item Conditions MIN. TYP. MAX. Unit
VDD VCLK
Supply Voltage Time Keeping Supply voltage Crystal Oscillation Frequency Pull-up Voltage for INTR, TMOUT pin INTR, TMOUT
2.7 2.0
5.0
6.0 6.0
V V kHz
fXT
VPUP
32.768 10
V
3
RP/RF/RS5C62
DC ELECTRICAL CHARACTERISTICS
Unless Noted, VSS=0V, VDD=5V10%, Topt=-20 to +70C, X'tal=32.768kHz, (R135k1/2), CG=10pF, CD=10pF
Limits Symbol Item Pin Name Conditions MIN. TYP. MAX. Unit
VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOL2 IILK IOZ1 IOZ2 IOZ3 IDD1
"H" input voltage "L" input voltage "H" input voltage
A0 to A3, D0 to D3 CS, RD, WR CE
2.2 -0.3 0.8VDD -0.3
VDD+0.3 0.8 VDD+0.3 0.2VDD
V V V V V
"L" input voltage "H" output voltage D0 to D3 "L" output voltage "L" output voltage Input leak current INTR, TMOUT A0 to A3, CE, CS, RD, WR D0 to D3 Output off leak current INTR, TMOUT INTR, TMOUT Consumption current for back-up VDD IOH1=-400A IOL1=2mA IOL2=2mA VILK=VDD or VSS VOZ1=VDD or VSS VOZ2=VDD VOZ3=10V VDD=2.5V, CE=L Others : OPEN VDD=5.5V, CE=H, CS=H, Output : OPEN Input : VDD or VSS VDD=2.5 to 5.5V Topt=25C
2.4 0.4 0.4 -1 -5 -2 -5 1 5 2 5 3
V V A A A A A
IDD2
Consumption current for stand-by
VDD
8
A
f
Oscillation frequency OSCIN drift for voltage drift OSCOUT
-1
1
ppm
4
RP/RF/RS5C62
AC ELECTRICAL CHARACTERISTICS
VDD=5V10% Symbol Item MIN. MAX. MIN. MAX. MIN. VDD=3V10%
VSS=0V, Topt=-20 to +70C
VDD=5V20% Unit MAX.
tCES tCEH
CE Setup Time CE Hold Time
500 500 20 20 10 10 120 70 120 60 10
1,000 1,000 20 20 10 10 295 95 195 95 10
500 500 20 20 10 10 150 75 150 75 10
ns ns ns ns ns ns ns ns ns ns ns
tAS (RD) Address Setup Time (For Read) tAS (WR) Address Setup Time (For Write) tAH (RD) Address Hold Time (For Read) tAH (WR) Address Hold Time (For Write) tRR tRZ tW tDS tDH
Output Data Delay Time (CL=100pF) Output Data Floating Time Write Pulse Width Input Data Setup Time Input Data Hold Time
TIMING CHART
CE
tCES
A0 to A3
tCEH tAS(RD) tAH(RD)
CS Read RD
or
RD CS
D0 to D3 (Read Data)
tRR
Valid
tRZ
tAS(WR)
CS Write WR or WR CS
tW
tAH(WR)
D0 to D3 (Write Data)
tDS
Valid
tDH
*)
The diagonally shaded sections marked in the above timing chart indicate the allowable high or low levels of the CS, RD, and WR pin inputs.
Input/Output Conditions (VDD= 5V10%) VIH = 2.2V VIL = 0.8V VOH= 2.2V VOL = 0.8V (VDD= 3V10%) VIH = 0.8 VDD VIL = 0.2 VDD VOH= 0.8 VDD VOL = 0.2 VDD (VDD= 5V20%) VIH = 2.4V VIL = 0.4V VOH= 2.4V VOL = 0.4V
5
RP/RF/RS5C62
FUNCTIONAL DESCRIPTION
1. Addressing
Address Bus A3 A2 A1 A0 Description BANK 0 (BANK=0) D3 D2 D1 D0 Description BANK 1 (BANK=1) D3 D2 D1 D0
0 1 2 3 4 5 6 7 8 9 A B
0 0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0
0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1
1 sec. Counter 10 sec. Counter 1 min. Counter 10 min. Counter 1 hour Counter 10 hour Counter
R/W R/W R/W R/W R/W R/W
S8
S4 S40
S2 S20 M2 M20 H2 P/A or H20
S1 S10 M1 M10 H1 H10 W1 D1 D10 MO1
Cyclic interrupt select Reg. W/O Adust Reg. 1 min. alarm Reg. 10 min. alarm Reg. 1 hour alarm Reg. 10 hour alarm Reg. W/O R/W R/W R/W R/W
CT3
CT2
CT1
CT0 ADJ
M8
M4 M40
AM8
AM4 AM40
AM2 AM20 AH2 AP/A or AH20
AM1 AM10 AH1 AH10
H8
H4
AH8
AH4
day-of-the-week Counter R/W 1 day Counter 10 day Counter R/W R/W MO8 D8
W4 D4
W2 D2 D20
1 month Counter R/W 10 month Counter R/W 1 year Counter R/W
MO4
MO2
MO10 12/24 select Reg. Y8 Y4 Y2 Y1 Leap Year Reg.
W/O R/O R/W W/O LYE TM2 TM3 TM1 LY1
12/24 LY0
TM0
C
1
1
0
0
10 year Counter
R/W
Y80
Y40
Y20
Y10
Timer Clock Select Reg.
R/W R/O
TMFG TMR BANK
D E F
1 1 1
1 1 1
0 1 1
1 0 1
Control Reg. 1 Control Reg. 2 Control Reg. 3
W/O WTEN ALEN R/O R/W W/O TSTA BSY CTFG
TMR
BANK Control Reg. 1 Control Reg. 2 Control Reg. 3
W/O WTEN ALEN R/O R/W W/O TSTA BSY CTFG
ALFG
XSTP
ALFG
XSTP
TSTB WTRST
TSTB WTRST
*1) *2) *3) *4)
R/W bits can be read and written. R/O bits can only be read. W/O bits can only be written. It is no problem to attempt writing to R/O bits and blank bits, but the attempt will fail. If W/O bits and blank bits are read, the returned value is 0. The control registers 1, 2, and 3 have the same address assignment for BANK0 and BANK1.
6
RP/RF/RS5C62
2. Functions of Registers
2.1 Control Register 1 (Bank0/1 at "Dh")
D3 WTEN 0 D2 ALEN 0 D1 TMR 0 D0 BANK 0 (For write operation) (For read operation) *1
Bank switching bit
BANK Function
0 1
Specifies selection of BANK0 in the address table. Specifies selection of BANK1 in the address table.
Timer resetting bit *2
TMR Function
0 1
Specifies no change. Specifies resetting of the timer conditional on restart.
Alarm operation setting bit *3
ALEN Function
0 1
Disables an alarm interrupt. Enables an alarm interrupt.
Time count operation setting bit *4
WTEN Function
0 1
Disables a carry to the 1-second time digit. Enables a carry to the 1-second time digit.
*1) *2) *3) *4)
The BANK bit is intended for only write operation and always read as "0". The timer frequency can be set by the timer clock selection register. Setting the ALEN bit to "0" during output of an alarm interrupt from the INTR pin (while it is held low) turns off the INTR pin. Setting the ALEN bit to "1" in matching between clock time and alarm time drives the INTR pin low within a maximum of 61.1s. A 1-second carry with the WTEN bit set to "0" increments the second digit by 1 upon setting of the WTEN bit to "1". This bit will automatically be set to "1" upon driving low the CE pin.
7
RP/RF/RS5C62
2.2 Control Register 2 (BANK0/1 at "Eh")
D3 D2 CTFG CTFG D1 ALFG ALFG D0 XSTP XSTP (For write operation) (For read operation)
**1
BSY
Oscillation stop detection bit *2
XSTP Function
0 1
Indicates the progress of oscillation. Intended for setting to "0". Indicates the stop of oscillation. Not intended for setting to "1".
Alarm time match indication bit *3
ALFG Function
0 1
Indicates an alarm interrupt is disabled or indicates mismatching between clock time and alarm time (upon turning off the INTR pin). Intended for setting to "0".
Indicates matching between clock time and alarm time (upon driving low the
INTR pin). Not intended for setting to "0".
Cyclic interrupt indication bit *4
CTFG Function
0 1
Indicates that the INTR pin is turned off. Intended for setting to "0" in the level mode. Indicates that the INTR pin is driven low. Not intended for setting to "0".
Time/calendar counter state indication bit *5
BSY Function
0 1
Indicates the normal state of the time and calendar counters (no carry or no reset pulse). Indicates the busy state of the time and calendar counters (a carry or a reset pulse generated).
*1) *2) *
The BSY bit is intended for only read operation and is not intended for write operation. The XSTP bit is used to detect the stop of the crystal oscillator. The XSTP bit is set to "1" upon the stop of oscillation and held at "1" after the restart of oscillation. Upon detection of the stop of oscillation, the built-in timer counter is reset (because the TM3 bit in the timer clock selection register is reset).
3) When the ALEN bit is set to "1", the ALFG bit is also set to "1" upon output of an alarm interrupt from the INTR pin (while it is held low).
8
RP/RF/RS5C62
ALFG INTR
Alarm time match
Alarm time match
Setting the ALFG bit to "0"
Alarm time match
*4)
The CTFG bit is set to "1" upon output of a cyclic interrupt from the INTR pin (while it is held low). (A cyclic interrupt may occur in the pulse mode and the level mode.)
Preset interrupt cycle
* Pulse mode
(The CT3 bit is set to "0".) (The CTFG bit is not intended for write operation.) INTR CTFG INTR CTFG
* Level mode
(The CT3 bit is set to "1".) (The CTFG bit is intended for setting to "0" only.)
Interrupt
Interrupt
Setting the CTFG bit to "0"
*5)
When the BSY bit is set to "1", write operation must not be performed upon the time and calendar counters which are being updated. Normally, read operation must be performed from the counters upon setting the BSY bit to "0". Reading from them without checking the BSY bit requires separate software for preventing reading errors. The BSY bit is set to "1" in the four cases below:
(I) Adjustment by 30 seconds
MAX.122.1s
Setting the ADJ bit to "1"
Completion of adjustment
(II) Correction by +1 (when there is a 1-second carry in transition of the WTEN bit from "0" to "1")
MAX.122.1s Setting the WTEN bit to "1" Completion of correction by +1
(III) Normal 1-second carry
91.6s
30.5s
Completion of pulse for carry to second digit
(IV) Counter resetting (setting of WTRST bit) (Resetting the 1 to 8Hz dividers)
MAX.122.1s Setting the WTRST bit to "1" Completion of reset
9
RP/RF/RS5C62
2.3 Control Register 3 (BANK0/1 at "Fh")
D3 TSTA 0 D2 TSTB 0 D1 WTRST 0 D0
** 1
0
(For write operation) (For read operation) *2
Bit for resetting lower-order counter than the second counter. *3
WTRST Function
0 1
Specifies normal operation. Specifies resetting of 1- to 8-Hz dividers conditional on restart.
Test mode setting bits *4
TSTA,TSTB Function
0 1
Specifies setting of the test mode. Specifies setting of normal operation.
*1) *2) *3) *
The bit marked with " " is not intended for write operation.
*
This bit is intended for only write operation and always read as "0". When set to "1", the WTRST bit specifies resetting of the lower-order counter than the 1 second counter ranging from 8Hz and 4Hz to 2Hz and 1Hz conditional on restart. The WTRST bit is used to adjust the lower-order counter than the 1 second counter. After the WTRST bit is set to "1", the BSY bit is set to "1" for a maximum of 122.1s.
4) Both the TSTA and TSTB bits must be set to "1" to specify normal operation and will automatically be set to "1" upon driving low the CE pin.
2.4 Adjustment Register (BANK1 at "1h")
D3 D2 D1 D0 ADJ 0 (For write operation) (For read operation) *2
** 1
0
*
0
*
0
Second digit adjustment bit *3
ADJ Function
0 1
Specifies normal operation. Specifies adjustment of second digit.
*1) *2) *3)
The bits marked with " " are not intended for write operation.
*
This bit is intended for only write operation and always read as "0". The ADJ bit is used to correct the second digit. When set to "1", the ADJ bit functions as follows: 1) For digits ranging from 00 seconds to 29 seconds (R) Resets the lower-order counter than the 1 second counter (in the same manner as the WTRST bit) and sets the second digit to "00". 2) For digits ranging from 30 seconds to 59 seconds (R) Resets the second and lower-order counters (in the same manner as the WTRST bit), sets the second digit to "00" and increments the minute digit by 1. The BSY bit is set to "1" for a maximum of 122.1s after the ADJ bit is set to "1".
10
RP/RF/RS5C62
2.5 Interrupt Cycle Selection Register (BANK1 at "0h")
D3 CT3 0 D2 CT2 0 D1 CT1 0 D0 CT0 0 (For write operation) (For read operation) *1
Interrupt cycle/output mode selection bits *2
*1) *2)
These bits are intended for only write operation and always read as "0". The CT3 to CT0 bits are used to set interrupt cycles and output modes as shown in the table below:
CT3
CT2
CT1
CT0
INTR
Remarks
* * * * * * * *
0 1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
"OFF" 2048Hz 1024Hz 128Hz 16Hz 1Hz 1/60Hz "ON" Pulse mode Level mode
Disable a cyclic interrupt. Specify a cycle (T) of 0.488ms (1/2048Hz). Specify a cycle (T) of 0.977ms (1/1024Hz). Specify a cycle (T) of 7.813ms (1/128Hz). Specify a cycle (T) of 62.5ms (1/16Hz). Specify a cycle (T) of 1s (1/1Hz). Specify a cycle (T) of 60s (1/1/60Hz). Specify the fixed low level of the INTR pin output. Specify a duty cycle of 50%. See below. See below.
* *
*
* *
* *
*)
The bits marked with " " are set to "0" or "1".
Preset interrupt cycle
* Pulse mode
(The CT3 bit is set to "0".) (The CTFG bit is not intended for write operation.)
CTFG INTR CTFG INTR
* Level mode
(The CT3 bit is set to "1".) (The CTFG bit is intended for setting to "0" only.)
Interrupt
(Interrupt) Setting the CTFG bit to "0"
* Relationship between INTR pin output and upward second count
(1) Pulse mode (when 1Hz or 1/60Hz is selected) INTR 30.5s Upward second count (2) Level mode (when 1Hz or 1/60Hz is selected) INTR 30.5s Upward second count Upward second count Upward second count
11
RP/RF/RS5C62
2.6 Alarm Register (1-minute, 10-minute, 1-hour, and 10-hour) (BANK1 at "2h to 5h")
D3 AM8 D2 AM4 AM40 AH4 D1 AM2 AM20 AH2 AP/A or AH20 D0 AM1 AM10 AH1 AH10 (For read and write operations) 1-minute alarm digit (at"2h") (For read and write operations) 10-minute alarm digit (at"3h") (For read and write operations) 1-hour alarm digit (at"4h") (For read and write operations) 10-hour alarm digit (at"5h")
*
AH8
*
*1) *2) *
*
The bits marked with " " are always read as "0" and not intended for write operation.
*
When enabling an alarm interrupt, non-existent minute and hour alarm digits must not be left (to prevent mismatching between clock time and alarm time).
3) Alarm minute and hour settings are exemplified in the table below:
Alarm minute and hour setting
12-hour time scale 10-hour digit 1-hour digit 10-minute 1-minute digit digit 10-hour digit
24-hour time scale 1-hour 10-minute 1-minute digit digit digit
0 : 00 a.m. 1 : 30 a.m. 11 : 59 a.m. 0 : 00 p.m. 1 : 30 p.m. 11 : 59 p.m.
1 0 1 3 2 3
2 1 1 2 1 1
0 3 5 0 3 5
0 0 9 0 0 9
0 0 1 1 1 2
0 1 1 2 3 3
0 3 5 0 3 5
0 0 9 0 0 9
*4)
In the the 12-hour time scale, the hour digits of 12 and 32 indicate 0 o'clock a.m. and 0 o'clock p.m., respectively.
2.7 12/24-hour Time Scale Selection Register (BANK1 at "Ah")
D3 D2 D1 D0 12/24 0 (For write operation) (For read operation) *2
**1
0
*
0
*
0
12/24-hour time scale selection bit *3,4
12/24 Function
0 1
Selects the 12-hour time scale with a.m. and p.m. indications. Selects the 24-hour time scale.
*1) *2) *3)
The bits marked with " " are not intended for write operation.
*
These bits are intended for only write operation and always read as "0". The time digits are indicated in binary-coded decimal (BCD) notation as shown in the table below:
12
RP/RF/RS5C62
24-hour time scale 12-hour time scale 12-hour time scale 24-hour time scale
00 01 02 03 04 05 06 07 08 09 10 11
12 (AM12) 01 (AM 1) 02 (AM 2) 03 (AM 3) 04 (AM 4) 05 (AM 5) 06 (AM 6) 07 (AM 7) 08 (AM 8) 09 (AM 9) 10 (AM10) 11 (AM11)
12 13 14 15 16 17 18 19 20 21 22 23
32 (PM12) 21 (PM 1) 22 (PM 2) 23 (PM 3) 24 (PM 4) 25 (PM 5) 26 (PM 6) 27 (PM 7) 28 (PM 8) 29 (PM 9) 30 (PM10) 31 (PM11)
*4)
The 12-hour or 24-hour time scale must be selected before time of day adjustment or alarm time setting (e.g. at the time of initialization after power-on from 0V)
2.8 Leap Year Indication Register (BANK1 at "Bh")
D3 D2 LYE LYE D1 D0
**1
0
*
LY1
*
LY0
(For write operation) (For read operation)
Leap year indication bits (intended for only read operation) *2
(LY1,LY0) Function
(0,0) Any other value
Specifies leap year indication (including February 29) (when the LYE bit is set to "0". Specifies normal year indication (not including February 29).
Leap year indication selection bit *3,4
LYE Function
0 1
Enables leap year indication. Disables leap year indication.
*1) *2) *3) *
The bits marked with " " are not intended for write operation.
*
The LY1 and LY0 bits cycle from "00" via "01" and "10" to "11" with the passage of years. Upon setting the LYE bit to "0", automatic correction is made for leap years in the years 1901 to 2099 (e.g. 1992, 1996, and 2000). Upon setting the LYE bit to "1", leap year indication is disabled (counting up to February 28).
4) Writing to the 1-year or 10-year counter enables leap year indication (sets the LYE bit to "0").
13
RP/RF/RS5C62
2.9 Timer Clock Selection Register (BANK1 at "Ch")
D3 TM3 TM3 D2 TM2 0 D1 TM1 0 D0 TM0 TMFG (For write operation) (For read operation) *1
Timer counter cycle setting bit (TM3 to TM0) *2 Timer output indication bit (TMFG) *3
*1) *2)
Only the TM3 bit is intended for read operation. The D0 bit is always read as "TMFG". The D2 and D1 bits are always read as "0". The TM3 to TM0 bits are used to set cycles for the counters as shown in the table below.
TM3
TM2
TM1
TM0
T1
(Watchdog timer cycle)
T2
T3
(Output time after timer resetting) (Free-running timer cycle)
0 1 1 1 1 1 1 1 1
Timer output disabled
Timer output disabled
(TMOUT pin output turned off)
Timer output disabled
(TMOUT pin output turned off)
*
0 0 0 0 1 1 1 1
*
0 0 1 1 0 0 1 1
*
0 1 0 1 0 1 0 1
(TMOUT pin output turned off)
562ms 281ms 140ms 70.3ms 35.1ms 17.5ms 8.78ms 4.39ms
562 to 626ms 281 to 313ms 140 to 157ms 70.3 to 78.2ms 35.1 to 39.1ms 17.5 to 19.6ms 8.78 to 9.77ms 4.39 to 4.89ms
625ms 312.5ms 156.3ms 78.13ms 39.06ms 19.53ms 9.766ms 4.883ms
T1 : Maximum time during which timer output is disabled after timer resetting. (Timer reset occurs upon setting the TMR bit to "1" in the control register 1.) (Timer output occurs upon driving low the TMOUT pin output.) T2 : Time between timer output and cycle setting during timer resetting (upon setting the TM3 bit to "0" ), or timer resetting, or transition of the CE pin input from its low to high levels. T3 : Timer output cycle without timer reset.
14
RP/RF/RS5C62
*3)
Relationship between TMFG Bit and TMOUT pin output
TMOUT 0.244ms TMFG MAX.T1 Setting the TMR bit to "1" T2 T3
Setting the TMR bit to "1"
*4) *5) *
The timer is stopped (the TMOUT pin output is turned off) upon driving low the CE pin input, but restarted upon driving high the CE pin input. Timer output is disabled (the TMOUT pin output is turned off) upon resetting the TM3 bit to "0" when the stop of oscillation is detected (setting the XSTP bit to "1").
6) Timer output is turned off (the TMOUT pin output is turned off) upon setting the TMR bit to "1" in the control register 1 during timer output (while the TMOUT pin is held low).
3. Functions of Counters
3.1 Time Counter (BANK0 at "0h to 5h")
D3 S8 D2 S4 S40 M4 M40 H4 D1 S2 S20 M2 M20 H2 P/A or H20 D0 S1 S10 M1 M10 H1 H10 (For read and write operations) 1-second time digit (at "0h") (For read and write operations) 10-second time digit (at"1h") (For read and write operations) 1-minute time digit (at"2h") (For read and write operations) 10-minute time digit (at"3h") (For read and write operations) 1-hour time digit (at "4h") (For read and write operations) 10-hour time digit (at"5h")
*
M8
*
H8
*
*
*1) *2) *3)
The bits marked with " " are always read as "0" and not intended for write operation.
*
Upon setting the WTEN bit to "0" in the control register 1, a carry to the 1-second time digit from the second counter is disabled. The time digits are indicated in BCD notation as shown below: Second digit: Ranges from 00 to 59 and carried to the minute digit in transition from 59 to 00. Minute digit: Ranges from 00 to 59 and carried to the hour digit in transition from 59 to 00. Hour digit: Ranges as shown in "2. 7 12/24-hour Time Scale Selection Register" and carried to the day or day-of-the-week digit in transition from 11 p.m. to 12 a.m. or from 23 to 00.
*
4) A carry from any non-existent time digit must be avoided because it may cause malfunction in the time counter.
15
RP/RF/RS5C62
3.2 Day-of-the-week Counter (BANK0 at "6h")
D3 D2 W4 D1 W2 D0 W1 (For read and write operations) Day-of-the-week counter
*
*1) *2) *3) *
The bits marked with " " are always read as "0" and not intended for write operation.
*
The day-of-the-week counter is incremented by 1 in a carry to the 1-day calendar digit. Days of the week written to the W4, W2, and W1 bits are counted up in septimal notation as shown below : (000)(R)(001)(R) ..... (R)(110)(R)(000) The correspondence between days of the week and readings of the day-of-the-week counter is user-definable (e.g. Sunday=000)
4) The W4, W2, and W1 bits must not be all set to 1.
3.3 Calendar Counter (BANK0 at "7h" to "Ch")
D3 D8 D2 D4 D1 D2 D20 MO2 D0 D1 D10 MO1 MO10 Y1 Y10 (For read and write operations) 1-day calendar digit (at"7h") (For read and write operations) 10-day calendar digit (at"8h") (For read and write operations) 1-month calendar digit (at"9h") (For read and write operations) 10-month calendar digit (at"Ah") (For read and write operations) 1-year calendar digit (at"Bh") (For read and write operations) 10-year calendar digit (at"Ch")
** *
1
*
MO4
MO8
*
Y4 Y40
*
Y2 Y20
Y8 Y80
*1) *2)
The bits marked with " " are always read as "0" and not intended for write operation.
*
The calendar digits are indicated in BCD notation by the automatic calendar function as shown below:
Day digit
: Ranges from 1 to 31 (in January, March, May, July, August, October, and December) Ranges from 1 to 30 (in April, June, September, and November) Ranges from 1 to 29 (in February in leap years) Ranges from 1 to 28 (in February in normal years) Carried to the month digit in transition back to 1.
Month digit : Ranges from 1 to 12 carried to the year digit in transition back to 1. Year digit : Ranges from 00 to 99 including leap years of 00, 04, 08, - - - - - -, 92, and 96 (when leap year indication is enabled by setting the LYE bit in the leap year indication register to "0" ).
*3)
A carry from any non-existent calendar digit must be avoided because it may cause malfunction in the calendar counter.
16
RP/RF/RS5C62
USAGE
1. Reading and Writing Operations
Upon driving high the CE pin, the interfacing input/outCE A3 to A0 RD CS WR D3 to D0 Writing operation Data bus Address Reading operation
put pins are enabled, establishing equivalence in logic between the RD and CS pin inputs during read operation and between the WR and CS pin inputs during write operation. Upon driving low the CE pin, the interfacing input/output pins are disabled, preventing occurrence of invalid leak current due to their floating. The CE pin must always be driven either high or low and must never be left floating.
1.1 Reading Operation
The requirements for reading data from the internal registers and counters are: [1] holding the CE pin high, [2] performing the process of addressing through the A3 to A0 pin inputs, then [3] driving low the CS pin, [4] causing the RD pin to transition from its high to low levels, and thereby [5] causing the D3 to D0 pins to output read data. The reading timing is shown in the chart below.
[1]
CE
tCES
A0 to A3
[2]
tCEH tAS(RD) tAH(RD)
CS RD
or
RD CS
[3] [4]
D0 to D3 (Read Data)
tRR
Valid
[5]
tRZ
*1) *
The CS and RD pin inputs are interchangeable. The diagonally shaded sections marked in the above timing chart may be set to both high and low levels. (Consequently, the CS and RD pin inputs may be caused to transition from their high to low levels before the process of addressing.)
2) "tAS (RD)" indicates the time required to perform the process of addressing before the start of read operation at which both the RD and CS pin inputs are driven low.
*3)
"tAH (RD)"indicates the time required to maintain the result of addressing after the completion of read operation at which either the RD or CS pin input is driven high.
17
RP/RF/RS5C62
1.2 Writing Operation
The requirements for writing data to the internal registers and counters are: [1] holding the CE pin high, [2] performing the process of addressing through the A3 to A0 pin inputs, then [3] driving low the CS pin, [4] causing the WR pin to transition from its high to low to high levels, and thereby [5] causing the D3 to D0 pins to input data to be written. The writing timing is shown in the chart below.
[1]
CE
tCES
A0 to A3
[2]
tCEH tW tAH(WR)
tAS(WR)
CS WR or WR CS
[4] [3]
D0 to D3 (Write Data)
tDS
Valid
[5]
tDH
*1) * *
The CS and WR pin inputs are interchangeable. The diagonally shaded sections marked in the above timing chart may be set to both high and low levels. (Consequently, the CS and WR pin inputs may be caused to transition from their high to low levels before the process of addressing.)
2) "tAS (WR)" indicates the time required to perform the process of addressing before the start of write operation at which both the WR and CS pin inputs are driven low. 3) "tAH (WR)" indicates the time required to maintain the result of addressing after the completion of write operation at which either the WR or CS pin input is driven high.
2. Handling of CE Pin
Normally, the CE pin is connected to the supply voltage detection circuit of the system power supply. In switching the system power supply (see the typical power supply circuit), the CE pin must be driven low before the voltage across the system power supply drops below the lower limit to the operating voltage of the CPU (at the point ( [1] ) in the timing chart below) and then driven high after the supply voltage rises above the lower limit to the operating voltage of the CPU (at the point ( [2] ) in the timing chart below).
VDD
Voltage across system power supply
Lower limit to operating voltage of CPU
[1] [2]
Battery voltage
CE 0.2VDD MIN.0s 0.2VDD MIN.0s
*)
The CE pin must be driven as low as the VSS pin whenever possible in order to minimize battery consumption in battery backup (while the CE pin is held low).
18
RP/RF/RS5C62
3. Configuration of Oscillatory Circuit
Typical external components:
RP/RF/RS5C62 RD RF
VDD OSCOUT CD 32kHz OSCIN A CG
VDD
X'tal : 32.768 kHz R1 35k1/2 CG=5pF to 35pF CD=5pF to 35pF Standard values of internal elements: RF=12M1/2 RD=60k1/2
In the oscillatory circuit, which is driven by a constant voltage of about 2V relative to the VDD pin, either one end of the oscillatory capacitors CG and CD must be connected to the VDD pin without exception.
Reference
When either one end of the oscillatory capacitors CG and CD is connected to the VSS pin instead of the VDD pin, the oscillatory circuit is still operational but subject directly to fluctuations in the voltage of the system power supply. Under sharp fluctuations between 5V and battery voltage in particular, the oscillatory circuit may be brought to a temporary stop. Thus, it is not recommendable to connect either one end of the oscillatory capacitors CG and CD to the VSS pin.
< Considerations in Installing Components Surrounding Oscillatory Circuit >
1) Install the oscillatory capacitors CG and CD in the closest possible proximity to the IC. 2) Avoid laying any signal or power line in the proximity of the oscillatory circuit (particularly in the area marked with "A(R)" in the above figure). 3) Apply the highest possible insulation resistance between the OSCIN or OSCOUT pin and the printed circuit board (PCB). 4) Avoid using any long parallel line to wire the OSCIN and OSCOUT pin. 5) Take extreme care not to cause condensation, which leads to various problems such as failure of the crystal oscillators.
< Other Relevant Considerations >
1) When applying an external input of clock pulses (32.768kHz) to the OSCIN pin: DC coupling ...........Prohibited due to mismatching input levels. AC coupling ...........Permissible except that unpredictable results may occur upon detection of the stop of oscillation if any error occurs in such detection due to such factors as noises. Timer operation is prohibited upon detection of the stop of oscillation. 2) Avoid using the oscillator output of the RP/RF/RS5C62 (from the OSCOUT pin) to drive any other IC for the purpose of ensuring stable oscillation characteristics.
19
RP/RF/RS5C62
4. Adjustment of Oscillation Frequencies
4.1 Measurement of Oscillation Frequency
The oscillation frequency can be measured by using the INTR pin output (a cyclic interrupt). Note that its measurement is affected by and cannot therefore be obtained with accuracy by the OSCIN pin input and the OSCOUT pin output, which are directly measured by such means as a probe.
VDD OSCOUT OSCIN CD CG
VDD
*1) *2) *3)
Use a frequency counter with 6 or more readout digits in order to ensure an accuracy on the order of 1ppm.
*3 *2
Pull up the INTR pin to the VDD and set the CE pin to high.
Connect either one end of the oscillatory capacitors CG and CD to the VDD pin.
INTR
Frequency counter
*
1
Power-on from 0V
Control register 3
Ch
*4
*4)
Set both the TSTA and TSTB bits to "1" in the control register 3 to disable the test circuit.
Control register 1
1h
*5
*5)
Set the ALEN bit to "0" and the BANK bit to "1" in the control register 1 to disable an alarm interrupt.
Control register 2
0h
*6
*6)
Set both the CTFG and ALFG bits to "0" in the control register 2 to disable an alarm interrupt and a cyclic interrupt.
Interrupt cycle selection register
5h
*7
*7)
Set a cyclic interrupt to 1Hz (or any other cycle) in the pulse mode.
*8)
Read frequency counter
An error of 1ppm for every 1Hz amounts to a time lag of approximately 2.6 seconds per month. [Example of monthly time lag calculation given an error of 1ppm for every 1Hz. 1ppm x 60 seconds x 60 minutes x 24 hours x 30 days = 2.592 = approx. 2.6 seconds per month ]
*8
20
RP/RF/RS5C62
4.2 Adjustment of Oscillation Frequencies
Select crystal oscillators
*1
Select CG and CD < Unless adjustment needs to be made to oscillation frequencies: > < If adjustment needs to be made to oscillation frequencies: >
Fix CG and CD
Replace CG with trimmer capacitor
*2
Change ranking of oscillation frequencies
Fix trimmer capacitor
*4
NO
Optimize CG and CD YES END
*
3
Change ranking of oscillation frequencies
Optimize CD YES
NO
*3
Make fine adjustment to oscillation frequencies
END
*1) * *3)
In selecting crystal oscillators, inquire of their suppliers. Check how the selected crystal oscillators match the RP/RF/RS 5C62 and determine the ranking of oscillation frequencies (load capacitance (CL) in general and equivalent series resistance (R1).)
2) The oscillatory capacitor CD can be replaced with a trimmer capacitor to adjust oscillation frequencies. Optimize the oscillatory capacitors CG and CD to adjust oscillation frequencies to desired values (on the actual PCB in consideration of possible influences by floating capacitance). Note that the greater capacitance of the oscillatory capacitors CG and CD tend to result in increased current consumption and prolonged oscillation start time. As a guide, their recommendable capacitance ranges from 5 pF to 20 pF (10 pF to 10-odd pF in particular). (See the typical characteristic measurement.)
*
4) Set the rotational angle of the trimmer capacitor slightly below the central value in its adjustment range (to ensure matching between the central values of the rotational angle and oscillation frequencies in consideration of the fact that smaller capacitance lead to greater frequency variations).
Oscillation frequencies are subject to variations due to possible fluctuations in ambient temperature and supply voltage (see "Typical Characteristics").
Reference
A 32kHz crystal oscillator causes a clock delay above or below the central temperature range of 20C to 25C. It is therefore recommended to adjust or set oscillation frequencies in such a manner as to become slightly high in room temperature.
21
RP/RF/RS5C62
5. Interrupts
Interrupts are available in the following two types: 1) Alarm interrupt: Requested upon driving low (turning on) the INTR pin in matching between preset alarm time (in minutes and hours) and time indicated by the time counter (in minutes and hours). 2) Cyclic interrupt: Requested upon driving low (turning on) the INTR pin with a preset cycle. To output an alarm interrupt and a cyclic interrupt, the INTR pin is configured as shown in the figure below:
INTR Alarm interrupt Cyclic interrupt
*1) * *3)
When an alarm interrupt and a cyclic interrupt are generated in combination, their logical sum (OR) is output from the INTR pin. In this event, they can be distinguished from each other by reading the ALFG and CTFG bits of the control register 2.
2) The INTR pin output has indefinite states at power-on from 0V. An alarm interrupt and a cyclic interrupt are both enabled whether the CE pin input is held high or low.
Interrupt Registers Alarm-time ................Alarm register ALEN bi ALFG bit Cyclic .......................Cyclic interrupt select register CTFG bit (See "2. 6 Alarm Register".) (See "2. 1 Control Register 1".) (See "2. 2 Control Register 2".) (See "2. 5 Control Register 2".) (See "2. 2 Control Register 2".)
5.1 Alarm Interrupt
Desired alarm time (in minutes and hours) can be preset in the alarm digits of the alarm register with the ALEN bit set to "0" and then to "1" in the control register 1. Upon matching between the preset alarm time and the time indicated by the time counter, the INTR pin is driven low (turned on) to output a request for an alarm interrupt. The INTR pin output can be controlled by using the ALEN bit in the control register 1 and the ALFG bit in the control register 2.
Alarm time match period: 1 minute MAX.61.1s INTR ALEN=1 Alarm time match ALEN=0 ALEN=1 ALEN=0 Alarm time match
INTR
ALEN=1 Alarm time match ALFG=0
Alarm time match
*1) *2)
The above figure assumes that an alarm interrupt occurs in the absence of a cyclic interrupt. The ALFG bit has an inverse logic from that of the INTR pin output.
22
RP/RF/RS5C62
5.2 Cyclic Interrupt
A desired interrupt cycle can be preset in the bits in the interrupt cycle selection register. With the preset interrupt cycle, the INTR pin is driven low (turned on) to output an request for a cyclic interrupt. A cyclic interrupt can be output from the INTR pin in the pulse mode and the level mode. In the level mode in particular, a cyclic interrupt can be disabled by setting the CTFG bit to "0" in the control register 2. Available interrupt cycles: 6 types (0.488ms, 0.977ms, 7.813ms, 62.5ms, 1s, and 60s) Available output modes: 2 types (pulse mode and level mode)
Preset interrupt cycle CTFG INTR CTFG
* Pulse mode
(The CT3 bit is set to "0".) (The CTFG bit is not intended for write operation.)
* Level mode
(The CT3 bit is set to "1".) (The CTFG bit is intended for setting to "0" only.) Interrupt (Interrupt) Setting the CTFG bit to "0" INTR
*1) *2) *3)
A preset interrupt cycle can be canceled by setting the bits to "0" in the interrupt cycle selection register. The above figure assumes that a cyclic interrupt occurs in the absence of an alarm interrupt. The CTFG bit has an inverse logic from that of the INTR pin output.
Cyclic Interrupt Interrupt cycle selection register CTFG bit (See "2.5 Interrupt Cycle Selection Register") (See "2.2 Control Register 2")
6. Timer
Upon lapse of time preset in the timer clock selection register, cyclic pulses are output from the TMOUT pin. The timer counter can be reset conditional on restart by setting the TMR bit to "1" in the control register 1. (It can act as a watchdog timer.)
TMOUT 0.244ms TMFG MAX.T1 Setting the TMR bit to "1" T2 T3
Setting the TMR bit to "1"
*1) *2) *3) *4)
The timer is stopped upon driving low the CE pin input, but restarted upon driving high the CE pin input. Timer output is disabled upon resetting the TM3 bit to "0" when the stop of oscillation is detected. The T3 to T1 bits are described in "2. 9 Timer Clock Selection Register". Timer output is turned off upon setting the TMR bit to "1" in the control register 1 during timer output.
23
RP/RF/RS5C62
Reference
It is recommended to update the settings of the timer clock selection register at regular time intervals to improve the stability of timer operation.
Elements Involved in Timer Timer clock selection register and TMFG bit TMR bit (See "2.9 Timer Clock Selection Register") (See "2.1 Control Register 1")
7. Detection of Stop of Oscillation
The stop of oscillation can be detected by monitoring the XSTP bit in the control register 2. Namely, the XSTP bit is switched from "0" to "1" upon detection of the stop of oscillation. This principle can be used to check the validity of time data. (The stop of oscillation can also be detected by using the software-controlled processes described in 11.1.2 Initialization Subject to Setting of XSTP Bit. "Initialization at Power-on".)
XSTP Power-on from 0V *1 Stop of oscillation Restart of oscillation *2
Setting the XSTP bit to "0" (During oscillation)
*1) *2)
The XSTP bit is set to "1" at power-on from 0V. Note that the XSTP bit may be locked at instantaneous power disconnection. Once the stop of oscillation has been detected, the XSTP bit is kept at "1" even after the restart of oscillation.
Considerations in Using XSTP Bit
Ensure error-free detection of the stop of oscillation by: 1) Preventing the VDD pin input from making instantaneous power disconnection. 2) Preventing the crystal oscillators causing condensation. 3) Preventing the crystal oscillators from causing noises on the PCB. 4) Preventing the individual pins from being impressed with voltage exceeding the maximum rating.
24
RP/RF/RS5C62
8. Typical Power Supply Circuit
Voltage of system power supply
1) Connect either one end of the oscillatory capacitors CG and CD to the VDD pin. 2) Install the by-pass capacitors for both high and low frequencies in close proximity to the IC in such a manner as to form a parallel arrangement. 3) Connect the pull-up resistor of the INTR pin to different points depending on whether it is used while the CE pin is held low (in battery backup). (I) Connect the pull-up resistor to Point A in the left circuit diagram unless it is used while the CE pin is held low. (II) Connect the pull-up resistor to Point B in the left
RP/RF/RS5C62 A INTR OSCIN OSCOUT VDD B
VSS
circuit diagram if it is used while the CE pin is held low.
25
RP/RF/RS5C62
9. Typical Connection between RP/RF/RS5C62 and CPU
RP/RF/RS5C62 and CPU Z80
Z80 A4 to A15 IORQ A3 to A0 D3 to D0 RD WR Address Decoder RP/RF/RS5C62
RP/RF/RS5C62 and CPU 6809
6809 A4 to A15 BS BA Address Decoder RP/RF/RS5C62
CS A3 to A0 D3 to D0 RD WR
CS
A3 to A0 D3 to D0 R/W E
A3 to A0 D3 to D0 RD WR
Powerdown Detector
CE
Powerdown Detector
CE
RP/RF/RS5C62 and CPU 8086
8086 Address Decoder RP/RF/RS5C62 CS A3 to A0 ALE A0 to A19 BHE AD0 to 15 RD WR Powerdown Detector A0 to A19
RP/RF/RS5C62 and CPU 68000
68000 A1 to A23 BG RP/RF/RS5C62 Address Decoder CS A3 to A0 D3 to D0 D3 to D0
BHE Latch D3 to D0 RD WR CE WR Powerdown Detector R/W LDS RD WR
CE
26
RP/RF/RS5C62
10. Typical Characteristics
VDD CD VDD OSCOUT A X'tal OSCIN VSS INTR CG CD=10pF, CG=10pF X'tal : RL35k1/2 Topt=25C Input pin : VDD or VSS Output pin : Open
Frequency counter
10.1 Current Consumption vs. CD
4 Current Consumption IDD(A) CD= 5pF CD=10pF CD=20pF CD=30pF CD=39pF VDD=3V
10.2 Current Consumption vs. CG
4 Current Consumption IDD(A) VDD=3V CD= 5pF CD=10pF CD=20pF CD=30pF CD=39pF
3
3
2
2
1
1
0
0
10
20 CD(pF)
30
40
0
0
10
20 CG(pF)
30
40
10.3 Current Consumption vs. VDD
Topt=25C CG=CD=10pF
10.4 Current Consumption vs. Temperature
VDD=3V CG=CD=10pF
4 Current Consumption IDD(A)
4 Current Consumption IDD(A)
3
3
2
2
1
1
0
0
1
2
3 VDD(V)
4
5
6
0 -40
-20
0 20 40 Temperature Topt(C)
60
80
27
RP/RF/RS5C62
10.5 Oscillation Frequency vs. CG
f0:CG=CD=10pF VDD=3V
10.6 Oscillation Frequency vs. CD
f0:CG=CD=10pF VDD=3V
80 60 40 Df/fo(ppm)
80 60 40 Df/fo(ppm) 20 0 -20 -40 -60 -80
20 0 -20 -40 -60 -80 -100 CD=30pF 0 10 20 CG(pF) 30 40 CD=10pF CD=20pF CD= 5pF
CD= 5pF CD=10pF CD=20pF CD=30pF 0 10 20 CD(pF) 30 40
-100
10.7 Oscillation Frequency vs. VDD
f0:VDD=4V CG=CD=10pF
10.8 Oscillation Frequency vs. Temperature
f0:Topt=22.5C VDD=3V,CG=CD=10pF
1
10
0
0 Df/fo(ppm) -1 -2 -10 -20 -30 -40 -50 -60 -4 0 1 2 3 4 VDD(V) 5 6 -70 -20 0 20 40 Topt(C) 60 80
Df/fo(ppm)
-3
10.9 Oscillation Start Time vs. CG
3 2.5 2 1.5 1 0.5 -4 CD= 5pF CD=10pF CD=20pF CD=30pF CD=39pF VDD=3V
10.10 Nch Open Drain Output IDS vs.VDS
35 30 VDD=5V 25 IDS(mA) 20 VDD=3V 15 10 5
Oscillation start time (s)
0
10
20 CG(pF)
30
40
0
0
0.5
1 VDS(V)
1.5
2
28
RP/RF/RS5C62
11. Typical Software-controlled Processes
11.1 Initialization at Power-on
At power-on from 0V, the internal registers and the output pins have indefinite states and therefore require initialization. The process of initialization differs as exemplified below depending on whether the XSTP bit (oscillation stop detection bit) is set in the control register 2. In the latter typical process of initialization below, the XSTP bit is used to check the validity of internal time data and the presence or absence of the initial routine.
11.1-1 Initialization Subject to No Setting of XSTP Bit
Start
*1)
Power-on from 0V
At power-on from 0V, the internal registers and the output pins have indefinite states.
*
Fh
1
Control register 3
*2 *3
*2)
Set both the TSTA and TSTB bits and the WTRST bit to "1" in the control register 3 and thereby set the BSY bit to"1" in the control register 2.
Control register 1
3h
*3)
Control register 2 0h
Set the WTEN bit to "0" (clock operation disabled), the ALEN bit to "0" and TMR bit to "1" ( turn off the output pins) and the BANK bit to "1" in
*4
the control register 1.
Timer clock selection register
0h
*4) *5)
*5
NO Wait
Drive high (turn off) the INTR and TMOUT pin outputs.
Interrupt cycle selection register
0h
Check the BSY bit in the control register 2 for the dual purpose of confirming the absence of a carry and confirming the start of oscillation. This requires additional time to wait for the start of the crystal oscillators. Fur-
BSY=0? YES
ther, assign a time-out period to exit from the loop for checking the BSY bit.
*6)
Set 12-hour or 24-hour time scale, time and calendar counters, interrupt cycles, and timer output cycles
Start both the clock and alarm functions.
*7)
This typical process of initialization is applied at power-on from 0V and not required at start-up from the backup battery.
Control register 1
Fh
*6
29
RP/RF/RS5C62
11.1-2 Initialization Subject to Setting of XSTP Bit
Start
*1)
*1 *2
Fh
At power-on from 0V, the internal registers and the output pins have indefinite states.
Power-on from 0V YES
* 2)
Check the validity of internal time data. In using the XSTP bit, ensure error-free detection of the stop of oscillation by:
XSTP=0? NO Control register 3
1) Preventing the crystal oscillators causing condensation. 2) Preventing the VDD pin input from making instantaneous power disconnection.
*3 *
4
3) Preventing the crystal oscillators from causing noises on the PCB (by such means as signal line isolation).
Control register 1
3h
4) Preventing the individual pins from being impressed with voltage exceeding the maximum rating.
Interrupt cycle selection register
0h
*5
* 3) * 4)
Wait
Set both the TSTA and TSTB bits and the WTRST bit to "1" in the control register 3 and thereby set the BSY bit to "1" in the control register 2.
BSY=0?
*6
NO
Set the WTEN bit to "0" (clock operation disabled), the ALEN bit to "0" and TMR bit to "1" ( turn off the output pins) and the BANK bit to "1" in the control register 1.
*9
YES
Control register 2
0h
*7
* 5) * 6)
Drive high (turn off) the INTR pin output.
Wait for the start of the crystal oscillators to confirm the start of oscillation as well as the absence of a carry. Further, assign a time-out period to exit from the loop for checking the BSY bit.
Set 12-hour or 24-hour time scale, time and calendar counters, interrupt cycles, and timer output cycles
* 7)
*8
Set the XSTP bit to "0" in the control register 2.
Control register 1
Fh
* 8) * 9)
Start both the clock and alarm functions.
This route is applied at start-up from the backup battery when the process of initialization is omitted, assuming no internal time data destruction.
30
RP/RF/RS5C62
11.2 Writing to or Reading from Time and Calendar Counters
Writing to the time and calendar counters must be performed in the absence of a carry. In particular, correct writing to the time and calendar counters requires stopping time count operation (by setting that the WTEN bit to "0" in the control register 1) and confirming the absence of a carry (by checking that the BSY bit to "0" in the control register 2). On the other hand, reading from the time and calendar counters may be performed by stopping time count operation, generating a cyclic interrupt, or dual reading.
11.2-1 Writing to or Reading from Time and Calendar Counters by Stopping Time Count Operation (by Setting WTEN and checking BSY bits)
*1) * 2)
Set 12- or 24-hour time scale
Set the 12- or 24-hour time scale once before writing to the time and calendar counters (at the time of initialization after power-on from 0V).
Set the WTEN bit to "0" in the control register 1 to stop the second and higher-order digits.
*1
* 3)
When the BSY bit is set to "1" in the control register 2, continue reading from the time and calendar counters until it is set to "0" or wait for 122.1 s or more. When the BSY bit is set to "0", it is kept at "0" until the WTEN bit is set to "1" again in the control register 1.
WTEN BANK
0 0
*2
* 4)
Writing to the 1-year or 10-year counter automatically enables leap year indication. To disable leap year indication, write "4h" (set the LYE bit to "1" ) in the leap year indication register after setting the time and calen-
BSY=0? YES
*3
NO Wait
dar counters. Note that leap year indication is continued without correction until the year 2099.
*
5
Write to or read from time and calendar counters
*4
* 5)
When reading from the time and calendar counters, ensure that this route lasts within 1 second. If this route lasts within 1 second, the 1-second digit is incremented by 1 to correct a 1-second carry occurring during read operation upon setting the WTEN bit to "1" again in the control register 1. Note that the 1-second digit is also incremented by 1 to correct
WTEN
1
*6
more than one 1-second carry while the WTEN bit is kept at "0", resulting in a clock delay.
* 6)
Restart time count operation. (The WTEN bit will automatically be set to "1" in the control register 1 upon driving low the CE pin.)
* 7)
When writing to the time and calendar counters, be sure to check the BSY bit in the control register 2 by disabling a carry (by setting the WTEN bit to "0" ).
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RP/RF/RS5C62
11.2-2 Reading from Time and Calendar Counters by Generating Cyclic Interrupt
Output cyclic interrupt from INTR pin NO Proceed to interrupt from other ICs
This typical process of reading from the time and calendar counters is applied on the conditions below:
CTFG=0?
1) The INTR pin is set to the level mode (upon setting the CT3 to "1" in the interrupt cycle selection register). 2) The route marked with " 1" lasts within the time equivalent to a preset
*1
CTFG
YES 0
*
cycle minus 30.5s (for the purpose of preventing occurrence of an error due to a carry during reading from the time and calendar counters).
Read from time and calendar counters
11.2-3 Reading from Time and Calendar Counters by Dual Reading
Read 1-second digit
* 1)
*
1
A carry from the second digit starts with 1 second via 10 seconds,---and 1 year, and ends with 10 years. Consequently, reading from the time and calendar counters must also start with the 10-second digit (at
Read from the time and calendar counters (starting with address "1h" and ending with address "Ch")
*
2
address "1h" ) and end with the 10-year digit (at address "Ch" ).
* 2)
Read 1-second digit again
This route assumes that an error occurs due to a carry during reading from the time and calendar counters.
Dual readings match? YES
NO
11.3 Writing Alarm Time to Alarm Registers
ALEN BANK
0 1
* 1)
Non-existent alarm time may be set in the alarm register, provided that an alarm interrupt is disabled. To enable an alarm interrupt, existent alarm time must be set in the alarm register.
Write alarm time (in minutes and hours)
*1
ALEN
1
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RP/RF/RS5C62
11.4 Adjusting Second Digit by 30 Seconds
*1)
BANK 1
Upon setting the ADJ bit to "1" in the adjustment register, the second and lower-order 1 to 8Hz dividers are reset conditional on restart. At this time, when the INTR pin is held low for output of a cyclic interrupt with a cycle of 1 second or 60 seconds in the pulse mode, the INTR pin is turned off with the timing shown below:
ADJ
1
*1
OFF INTR L Maximum of 200s
*
2
Setting the ADJ bit to "1"
* 2)
11.5 Detecting Start of Oscillation
Power-on from 0V
Adjustment of the second digit by 30 seconds requires a maximum of 122.1s, during which the BSY bit is kept at "1" in the control register 2.
*1
* 1) * 2)
Wait
This typical process of detecting the start of oscillation is applied at power-on from 0V.
At power-on from 0V, the XSTP bit is set to "1" in the control register 2.
XSTP=0 NO YES XSTP 0
*2 *3
* 3)
Note that the start of oscillation normally requires a time period (oscillation start time) on the order of 0.1 to 2 seconds. Further, assign a timeout period to exit from loop for checking the XSTP bit in the control register 2.
Detect start of oscillation
Notice In using the XSTP bit, ensure error-free detection of the stop of oscillation by: 1) Preventing the crystal oscillators causing condensation. 2) Preventing the VDD pin input from making instantaneous power disconnection. 3) Preventing the crystal oscillators from causing noises on the PCB (by such means as signal line isolation). 4) Preventing the individual pins from being impressed with voltage exceeding the maximum rating.
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RP/RF/RS5C62
QUESTIONS AND ANSWERS ON USE
Below are listed questions and answers on using the RP/RF/RS5C62 under the following four categories: 1) Crystal oscillators 2) Hardware 3) Software 4) AC/DC electrical characteristics and others
Category Questions and Answers
1) Crystal oscillators
Question 1 : What are the causes of failure in adjustment of oscillation frequencies? (Subject to use of variable capacitors and adjustment of oscillation frequencies) Answer 1: For capacitance variations of about 5 to 30pF, oscillation frequency variations measure a little more than about 60ppm in real terms (see the graphs in 10.5 and 10.6 of "10. Typical Characteristics"). The possible causes of failure in adjustment of oscillation frequencies are: 1. Variations in the crystals, the capacitors, and the ICs outside the range of adjustment of capacitance variations, and 2. Mismatching between the central value of variations in these elements and that of the range of variations of variable capacitors. The possible corrective measures for the causes 1. and 2. above are : 1. Reviewing variations in the individual elements. (For reference, measurements of variations in the ICs are shown in Answer 3 below.), and 2. Adjusting oscillation frequencies according to the directions described in "4. Adjustment of Oscillation Frequencies" in "USAGE".
Question 2 : What are the causes of inaccurate time count operation? (Subject to use of fixed capacitors and no adjustment of oscillation frequencies) Answer 2: The possible causes of inaccurate time count operation are : 1. Mismatching between the capacitance of the oscillatory capacitors CG and CD and that of the crystals and the ICs, and 2. Too great floating capacitance present on the actual PCB to be neglected for the oscillatory capacitors CG and CD, which are adapted to the ICs and the ranking of oscillation frequencies (load capacitance (CL)). The possible corrective measures for the causes 1. and 2. above are : 1. Adjusting oscillation frequencies according to the directions described in "4. Adjustment of Oscillation Frequencies" in "USAGE", and 2. Reduce the capacitance of the oscillatory capacitors CG and CD by the equivalent of floating capacitance, which seems to vary from 1 to several pF depending on the layout of the PCB, or mount them on the actual PCB for final fixing.
34
RP/RF/RS5C62
Category
Questions and Answers
Question 3 : How many variation factors should be considered? (Subject to use of fixed capacitors and no adjustment of oscillation frequencies) 1. The possible factors behind oscillation frequency variations are : 1-1. Variations in frequencies of crystals, 1-2. Variations in oscillation characteristics of the ICs, 1-3. Variations in the external oscillatory capacitors CG and CD, and 1-4. Variations in floating capacitance present on the actual PCB. 2. On the other hand, the possible factors behind surrounding environment variations are : 2-1. Variations in ambient temperature, and 2-2. Variations in supply voltage. Variations in 1 - 1 to 1 - 4 are listed in the order of decreasing degree. The individual variations are described below : 1-1. Most crystals seem to have variations in their frequencies on the order of 20ppm while some crystals may have smaller variations. For variations in frequencies of individual crystals, inquire of their suppliers. 1-2. Sample measurements of variations in oscillation characteristics of the ICs are shown graphically on the next page. Note that these measurements are not guaranteed ones and are therefore intended for reference use only. 1-3. Variations in oscillation frequencies differ slightly depending on the capacitance of external oscillatory capacitors CG and CD. More specifically, the smaller the capacitance of CG and CD, the greater the variations in oscillation frequencies. Subject to no adjustment of oscillation frequencies, they should have small variations relative to their capacitance (see the graphs in 10.5 and 10.6 of "10. Typical Characteristics"). 1-4. Normally, variations in floating capacitance present on the actual PCB seem to be small enough to be negligible. 2-1. Variations in ambient temperature are dominantly affected by the temperature characteristics of fork-shaped crystal oscillators (forming an upward-facing quadratic curve) (see the graph in 10.8 of "10. Typical Characteristics"). 2-2. Because the oscillatory circuit inside the ICs is driven by constant voltage, Variations in oscillation frequencies due to variations in supply voltage measure0.5ppm or less on real terms at room temperature with the VDD pin input ranging from 2.5V to 5.5V (see the graph in 10.7 of "10. Typical Characteristics").
35
RP/RF/RS5C62
Category
Questions and Answers
Sample Measurements of Variations in Oscillation Characteristics of ICs ppm 10 5 0 -5 0 -10 LOT1 LOT2 5 10 15 20 Number of samples LOT3 LOT4 25 30 VDD: 5V at room temperature CG: Approx. 10.5pF, CD: Approx. 12.5pF Total of 54 ICs sampled from 6 lots for measurement Average variation: 0ppm Standard deviation: 0.630ppm
LOT5
LOT6
Question 4 : Why should you avoid connecting either end of the oscillatory capacitors CG and CD to the VSS pin instead of the VDD pin? Answer 4: Because the oscillatory circuit is driven by a constant voltage of 2V relative to the VDD pin, either one end of the oscillatory capacitors CG and CD must be connected to the VDD pin without exception. When either one end of the oscillatory capacitors CG and CD is connected to the VSS pin instead of the VDD pin, the oscillatory circuit is still operational but subject directly to fluctuations in the voltage of the system power supply. Under sharp fluctuations between 5V and battery voltage in particular, the oscillatory circuit may be brought to a temporary stop. Thus, it is not recommendable to connect either one end of the oscillatory capacitors CG and CD to the VSS pin. Question 5 : Synchroscopic observation of the OSCOUT pin output shows that it has an oscillatory waveform having a small amplitude or approximating to the VDD pin input. What is the cause of this phenomenon? Answer 5: To reduce power consumption, the oscillatory circuit is driven by a constant voltage of about 2V relative to the VDD pin, so that the OSCOUT pin output has an oscillatory waveform shown in the figure below. Its amplitude will vary slightly depending on the capacitance of the oscillatory capacitor CD. Note that the oscillatory waveform measurements on the OSCOUT pin cannot be directly applied to adjustment of oscillation frequencies, which are shifted by use of a probe. (For how to adjust oscillation frequencies, see "4. Adjustment of Oscillation Frequencies" in "USAGE".)
VDD Vp-p:Approx. 1.5 to 2.0V Approx. 2.0V
Internal constant voltage output
VSS
36
RP/RF/RS5C62
Category
Questions and Answers
2) Software
Question 1 : In the typical software-controlled process of initialization at power-on from 0V, the BSY bit is checked to find that it fails to be switched from "1" to "0". What is the cause of this failure? Answer 1: In the typical software-controller process of initialization at power-on from 0V, the BSY bit is set to "1" in the control register 2 by setting the WTRST bit to "1" in the control register 3 for the dual purpose of confirming the absence of a carry and confirming the start of oscillation. After power-on from 0V, the start of oscillation normally requires a time period (oscillation start time) on the order of 0.1 to 2 seconds, which, in turn, requires additional time to wait for the start of the crystal oscillators. It seems most likely, therefore, that the BSY bit fails to be switched from "1" to "0" due to prolonged oscillation start time. Further, another possibility is that the start of oscillation may be hindered by some trouble (e.g. condensation) with the crystal oscillators. It is necessary, therefore, to assign a time-out period to exit from the loop for checking the BSY bit in the control register 2. Question 2 : How is it possible to read from the time and calendar counters without setting the WTEN and BSY bits? Answer 2: As described in "11. 2. 1. Writing to or Reading from Time and Calendar Counters by Stopping Time Count Operation (by Setting WTEN and BSY Bits)", the WTEN bit in the control register 1 and the BSY bit in the control register 2 are used to read from the time and calendar counters in such a manner as to prevent occurrence of an error due to a carry during read operation. If the BSY bit is found to be "1", however, this typical software-controlled process involves additional time to wait for setting of the BSY bit to "0". To save such wait time, an alternative action can be taken to read the 1-second digit twice without setting the WTEN and BSY bits as shown in "11. 2. 3. Reading from Time and Calendar Counters by Dual Reading". This process features dual reading from the 1-second digit in anticipation of an error which may occur due to a carry during read operation from the time and calendar counters in case of mismatching between the dual readings. Question 3 : How can the INTR pin output be used? Answer 3: The INTR pin outputs an alarm interrupt and a cyclic interrupt. For details on these two types of interrupts, see "5. Interrupts" in "USAGE".
Question 4 : An attempt to disable an alarm interrupt by setting the ALFG bit to "0" in the control register 2 results in holding the INTR pin output low. What is the cause of this phenomenon? Answer 4: The INTR pin outputs the logical sum (OR) of an alarm interrupt and a cyclic interrupt when they are generated in combination. Consequently, an attempt to disable an alarm interrupt by setting the ALFG bit to "0" may result in holding the INTR pin low when it outputs a cyclic interrupt as well.
37
RP/RF/RS5C62
Category
Questions and Answers
Question 5 : An attempt to disable a cyclic interrupt by setting the CTFG bit to "0" in the control register 2 results in holding the INTR pin output low. What is the cause of this phenomenon? Answer 5: As in Answer 4 above, this phenomenon may occur when an alarm interrupt and a cyclic interrupt are simultaneously output from the INTR pin.
Question 6 : What will happen if non-existent time is set? Answer 6: Time or alarm digits which are non-existent or indicated in non-BCD notation can be set in the time counter or the alarm register without causing any trouble. If such invalid digits are left, however, they may cause faulty time count operation in case of a carry or mismatching between clock time and alarm time.
Question 7 : How can an alarm interrupt be used in battery backup? (Why is an alarm interrupt not output in battery backup?) Answer 7: An alarm interrupt is normally output from the INTR pin in battery backup (while the CE pin is held low). Its output is most likely to fail, therefore, when the other end of the pull-up resistor of the INTR pin is connected to any power supply which may be turned off. To prevent this problem, confirm that the other end of the pull-up resistor of the INTR pin is connected to the backup battery.
Question 8 : How can an alarm interrupt be output on a monthly basis? Answer 8: The RP/RF/RS5C62 are configured to issue a daily alarm and cannot be reconfigured to generate an alarm interrupt on a monthly basis. Considering that they are designed to reduce current consumption as described in "Note" below, an advisable alternative action is to generate an alarm interrupt to the CPU on a daily basis and keep track of alarm dates in a software-controlled process. Note : The RP/RF/RS5C62 are designed to reduce current consumption (ensure typical current consumption on the order of 1A for 3V). Daily current consumption can be calculated as follows : Assuming, for example, that an alarm interrupt to the CPU is generated on a daily basis as the CPU is operating for a period of 0.5seconds with peak current consumption of 20mA, daily current consumption can be calculated from the equation : 0.5s20mA/60 6024 = 0.115A. This means a total base current of a little more than 1A, a slight increase in current consumption.
38
RP/RF/RS5C62
Category
Questions and Answers
3) Hardware
Question 1 : Can the CS pin input be used as it is held low? Answer 1: The CS pin input can be used as it is held low, provided that the RD and WR pin inputs are caused to transition from their high to low to high levels to enable read and write operations, respectively.
Question 2 : May the CS pin input be driven low before or during the process of addressing? Answer 2: The CS pin input may be driven low before, during, or even after the process of addressing. Addressing time (tAS) indicates the time required to perform the process of addressing before the start of read or write operation at which both the RD and CS pin inputs or both the WR and CS pin inputs are driven low. For more details, see "1. Reading and Writing Operations" in "USAGE".
Question 3 : At power-on from 0V, the INTR pin is driven low to output interrupts. What is the cause of this phenomenon? Answer 3: At power-on from 0V, the internal registers and counters have indefinite states, causing the INTR pin to have indefinite states as well. It is necessary, therefore, to provide temporary masking for interrupts output from the INTR pin and initialize the internal registers and counters by following the typical software-controlled processes of initialization at power-on (see "11. 1 Initialization at Power-on"). (At power-on from 0V, when the XSTP bit is set to "1" to indicate the start of oscillation, the TMOUT pin output is turned off.)
Question 4 : As the N-channel open drain pins, may the INTR and TMOUT pins be impressed with higher voltage than the VDD pin? Answer 4: As the N-channel open drain pins, the INTR and TMOUT pins, neither of which incorporates a protective diode for the VDD pin, may be impressed with higher voltage than the VDD pin as long as it does not exceed the maximum absolute rating of 12V. Their on-state resistance typically ranges from a few dozen ohms to one hundred ohms (see the graph in 10.10 of "10. Typical Characteristics"). Their on-state current should preferably range from 10mA to 20mA or less and must not exceed the maximum current consumption for the package.
39
RP/RF/RS5C62
Category
Questions and Answers
Question 5 : Is it possible to configure a power switching circuit containing a diode? Answer 5: It is not recommendable to configure a power switching circuit containing a diode, which causes a voltage drop as shown in the right circuit diagram (where "D1" represents a diode). (The maximum absolute ratings of the input and output pins range from -0.3V to the VDD plus 0.3V.)
RP/RF/RS5C62 VDD D1
System power supply
Question 6 : To what test modes can the TSTA and TSTB bits be applied as test bits? Answer 6: The TSTA and TSTB bits are intended for IC selection and not for general users. (These test bits should be kept at "1" in normal operation and will automatically be set to "1" upon driving low the CE pin.)
Question 7 : What are the possible causes of any changes which may occur to internal time data? Answer 7: The possible causes of such changes include : 1. Occurrence of writing errors due to such factors as noises caused below the operating voltage of the CPU at the time of switching from the power supply to the backup battery, 2. Occurrence of instantaneous power disconnection, and 3. Writing to other addresses than are allocated originally due to shortage of addressing time (tAS). To cope with the cause 1. , see "2. Handling of CE Pin" in "USAGE". To solve the cause 2. , check the power supply system to prevent instantaneous power disconnection from occurring. To overcome the cause 3. , secure sufficient addressing time (tAS).
Question 8 : What are the ranges of operating voltages? Answer 8: Range of operating voltage of crystal oscillators only for time count operation: 2.0V to 6.0V. Range of operating voltage having any access to the CPU : 2.7V to 6.0V Incidentally, AC timing is available in three ratings : 3V10%, 5V10%, and 5V20%.
40
RP/RF/RS5C62
Category
Questions and Answers
4) AC/DC electric characteristics and others
Question 1 : What is the difference between backup current consumption and standby current consumption? Answer 1: Backup current consumption is defined as current consumption in battery backup with the CE pin held low (connected to the VSS input) and the other pins opened (the term "opened" also refers to "impressed with intermediate voltage"). On the other hand, standby current consumption is defined as current consumption in the absence of access from the CPU with the CE and CS pins held high (connected to the VDD pin input) and the other input pins connected to the VDD or VSS pin input and the other output pins opened. The VDD pin input is set to 2.5V for backup current consumption and 5.5V for standby current consumption.
Question 2 : How is it possible to know typical backup current consumption and temperature characteristics in determining the battery capacity? Answer 2: For typical backup current consumption and temperature characteristics, see the graphs in 10. 1 to 10.4 in "10. Typical Characteristics".
Question 3 : What is the cause of partial mismatching of AC timing with the high-speed CPU? Answer 3: AC timing is designed to secure margins including variations and therefore difficult to change in principle, provided that it is susceptible to change, as the case may be, upon request.
Question 4 : Is it possible to extend the operating temperature range of -20C to +70C? Answer 4: As in Answer 3 above, the operating temperature range is difficult to change in principle, provided that it is susceptible to change, as the case may be, upon request.
41
RP/RF/RS5C62
PACKAGE DIMENSIONS (Unit: mm/(inch))
* RP5C62 (18pin DIP)
24.8MAX. (0.976MAX.) 18 10 (0.259MAX.) 6.6MAX.
7.62TYP. (0.110MAX.) (0.185MAX.) (0.300TYP.) 2.8MIN. 4.7MAX.
1
9 (0.020)MIN.
MIN. 0.51
2.54TYP. (0.100TYP.)
1.5TYP. (0.300TYP.)
0.46 +0.15 -0.1 (0.018 +0.006 ) -0.004
o1
5
+0.15 0.25 -0.05 +0.006 (0.010-0.002 )
0
t
* RF5C62 (18pin SOP)
11.84MAX. 18 (0.466MAX.) 10
10.310.3 (0.092TYP) 2.34TYP.
+0.1 -0.05 +0.004 (0.010 ) -0.002
(0.4060.012) 7.49TYP. (0.295TYP.)
1.4TYP. (0.056TYP.)
1
9
1.27TYP. (0.050TYP.)
+0.1 -0.05 +0.001 (0.016TYP ) -0.002 0.41TYP
(0.0080.001)
0.20.1
0.25
0.660.2 (0.0260.008)
* RS5C62 (20pin SSOP)
6.5
20
+0.3 -0.1
11
4.40.2 1.150.1 0.10.1 1 0.45MAX. 0.65 10
0.15
+0.1 -0.05
6.40.3
0.1 0.220.1 0.1 M
0.50.2
0 to10
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RP/RF/RS5C62
TAPING SPECIFICATIONS (Unit: mm)
* RF5C62 (18pin SOP)
4.00.1 0.30.05 o1.550.05 2.00.1 1.750.1 11.50.1 5.50.05 6.7 8.00.1 2.7MAX. E1 E2 1.750.1 12.00.3 6.9 13.2 240.3
11.05 120.1 3.350.1 E1 E2
User Direction of Feed.
* RS5C62 (20pin SSOP)
+0.1 o1.5-0 4.00.1 2.00.05
0.30.1
User Direction of Feed.
43
RICOH COMPANY, LTD. ELECTRONIC DEVICES DIVISION
HEADQUARTERS 13-1, Himemuro-cho, Ikeda City, Osaka 563-8501, JAPAN Phone 81-727-53-1111 Fax 81-727-53-6011 YOKOHAMA OFFICE (International Sales) 3-2-3, Shin-Yokohama, Kohoku-ku, Yokohama City, Kanagawa 222-8530, JAPAN Phone 81-45-477-1697 Fax 81-45-477-1694 * 1695 http://www.ricoh.co.jp/LSI/english/
RICOH CORPORATION ELECTRONIC DEVICES DIVISION
SAN JOSE OFFICE 3001 Orchard Parkway, San Jose, CA 95134-2088, U.S.A. Phone 1-408-432-8800 Fax 1-408-432-8375

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